In the conventional optical proximity correction (OPC) method, after an engineer directly collects data necessary for an OPC task from a workstation, data format for the OPC task is calculated in an engineering computer. It is then inputted again to the work station. But, in this case, there is a danger that the OPC process is subject to the subjective determination of the engineer, and the possibility that the fabrication yield of a semiconductor device is significantly reduced, since a determined format by each process cannot be confirmed. The present invention relates to an OPC automation apparatus and manufacturing method of a semiconductor device using the same.
A computer simulation tool is used for engineers in the integrated circuit (IC) design of the semiconductor device in order to create a design diagram. At this time, in order to accurately implement a very large scale integration within a semiconductor substrate, a physical display or a layout of the designed circuit itself before moving on to silicone is required. Moreover, a computer aided design (CAD) tool supports the task so that designers might convert individual circuit components into forms which will be implemented within the integrated circuit.
Semiconductor devices have individual circuit components such as a gate, an element isolation film, an impurity diffusion regions, a capacitor, a bit line, metal wirings and contact plugs that interconnect those components. In order to produce a functional circuit, such semiconductor devices are designed by software programs like the CAD system according to a predetermined design rule of one set. At this time, a design rule that performs a specific processing and determines a design limit is determined. For example, in order not to affect each other with any undesirable method between semiconductor devices, the design rule defines an allowed space value between the semiconductor devices or the lines that interconnect devices. The design rule limit is often called a critical dimension (CD). Generally, the critical dimension of a specific circuit is defined with a minimum line width or with a minimum space between two lines. Consequently, the critical dimension determines the whole size of the semiconductor chip and the density of the integrated circuit.
If the integrated circuit is designed with this method, the step of implementing the design on the semiconductor substrate progresses to the fabrication process of the integrated circuit. Optical lithography used in this step is a widely known process in which geometric shapes are implemented on the surface of the silicon wafer. Generally, the optical lithography process is initiated with forming the photoresist layer on the upper surface of the semiconductor wafer. Then, pure light non-transparent opaque regions formed with a chrome pattern and pure optical transmission opening regions formed with a quartz substrate are disposed on the upper portion of the wafer, which is coated with a photoresist layer.
A light is irradiated on a mask from a visible light source or a UV light source, and the light passing through optical lenses including one or several lenses, filters and mirrors passes through the opening areas of the mask. The photoresist layer is exposed by the light including a mask image which is reduced after passing through the mask.
The exposed region or the non-exposed region of the photoresist layer is developed through chemical removal, if necessary. As a result, the photoresist pattern defines geometry structures, features, lines and the shapes of the layer on the upper portion of the semiconductor wafer. Then, the region of the lower portion of the wafer is etched with a photoresist pattern to form the semiconductor device.
However, as the critical dimensions of the integrated circuit become smaller and approach a limit resolution value of the lithography equipment, the consistency between the actually formed photoresist pattern and the design mask is significantly reduced. Particularly, it was observed that the pattern variation of the circuit regions depends on the proximity of the region for each other.
Therefore, in order to reproduce accurately a desirable image on the wafer after the photolithography, integrated circuits having a restricted complexity which is almost identical demand correction of the initial mask design in the optical proximity effect. The proximity effect is produced when the pattern regions in which a gap is maintained to be near are lithographed and transferred to a resistant layer on the wafer. The light-waves which pass through the region in which a gap is maintained to be near affect each other, and in the end, distorting pattern regions are finally transferred.
Another problem which occurs when the sizes and gap of region approaches to the resolution limit of a lithography tool has the tendency that corners (a concave part and a convex part) are overly exposed or insufficiently exposed due to the concentration or the shortage of the energy at each corner. Likewise, when big and small regions are transferred from the same mask pattern, other problems of the excessive exposure or the insufficient exposure of small regions occur.
Presently, there are many methods for overcoming the problem of the proximity effect. These methods include precompensating of mask line widths, change of the thickness of the photoresist layer, usage of photoregist processes of the multi layer, usage of the electron beam imaging with the optical imaging and, finally, adding additional regions to an initial mask pattern in order to compensate for the proximity effect. Among these methods, the final method is known as “optical proximity correction (OPC)”.
The additional regions that are added to the initial mask when the OPC is used are typically a low level resolution (that is, the dimension is below the resolution of an exposure tool). Accordingly, they are not transferred to the resistant layer. Instead, in order to improve the pattern transferred and compensate for the proximity effect, these interact with the initial pattern.
Presently, several publicly known OPMSs (OPC Procedure Management System) are useful for regulating the resolution of the mask in order to include OPC regions. However, the products available in these days have many restrictions in the point of view of accuracy, speed, amount of data and verification of the resultant OPC correction mask design. For example, when the OPC regions are added to the mask, the current products utilize a passively inputted result. Therefore, an exact hierarchical data format of the initial mask design cannot be maintained.
The OPC task is usually performed in the workstation. At this time, the engineer directly collects necessary data for the OPC task, and calculates data format for the OPC task in the engineer computer, and inputs it again to the workstation. But in this case, the process is subjective and there exists the possibility that the processing yield of the semiconductor device remarkably decreases as the format determined by each class cannot be confirmed.